“CMOS” refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on IC “chips” or “die”. CMOS logic uses a combination of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunication equipment, and signal processing equipment. Typical commercial CMOS ICs include millions (or hundreds of millions) of n-type and p-type MOSFETS.
Most CMOS IC manufacturers (aka, “fabs”) generate standardized process “flows” for generating CMOS ICs on monocrystalline silicon wafers. Each CMOS process flow includes a series of processing steps (e.g., material deposition, photolithographic exposure, and etching) that are required to produce a desired CMOS IC product. Standard CMOS process flows are typically developed to produce “normal” CMOS IC devices (i.e., CMOS IC devices that comprise mainly volatile n-type and p-type MOSFETS) using a minimum number of processing steps in order to minimize overall production costs. Significant effort is typically expended by each manufacturer to make their standard CMOS process flow as time and cost efficient as possible. Once a standard CMOS flow is optimized, it can typically be used to make a large number of CMOS IC designs by merely by providing a different set of photolithography masks for each IC design, and then repeating the standard CMOS process flow using the selected set of photolithography masks.
Although most standard CMOS process flows facilitate the inclusion of non-MOSFET circuit components into the CMOS IC products, a problem arises when a circuit design requires a circuit component that cannot be produced by the standard CMOS process flow. In this case, the CMOS process flow must be modified at great expense to include additional steps in order to produce the needed circuit component. It is therefore desirable to develop methods for producing the non-standard circuit component using the steps of the existing CMOS process flow.
Non-volatile memory (NVM) or “floating gate” cells represent one type of non-standard circuit component that is often needed in large scale CMOS ICs. In contrast to volatile (aka primary storage) memory such as typical n-type and p-type MOSFETs, which require continuous power to retain stored information, NVM cells are able to retain a stored state even when power to an IC is turned off, thereby allowing the IC to “remember” important operating conditions and information upon restart. Several types of NVM cells have been developed that can be produced with minimal changes to a standard CMOS process flow. One NVM cell that has a small floating gate capacitively coupled to the drain area is disclosed in U.S. Pat. No. 6,678,190. This NVM cell is a programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors. A problem with the PMOS NVM cells of U.S. Pat. No. 6,678,190 is that the disclosed structure is impractical for performing erase operations due to the large voltage on the control gate that is needed to stimulate electron back-tunneling from or hole injection to the floating gate—even for voltages approaching the breakdown of the N-well junction, the potential difference between the floating gate and N-well is smaller than several volts. Further, the symmetric arrangement of the NVM cell of U.S. Pat. No. 6,678,190 requires a select transistor to address the cell.
Another NVM cell that also includes two PMOS transistors is described in U.S. Pat. No. 7,078,761. The floating gate includes an extension acting as a control gate and located over a special N-well that is spaced from the source and drain of the NVM transistor. A problem with this arrangement is that, along with the two-PMOS arrangement, the special N-well requires additional space, thus making the overall cell size undesirably large. The NVM cell of U.S. Pat. No. 7,078,761 also has a problem similar to that of the NVM cell of U.S. Pat. No. 6,678,190 in that it requires a select transistor to address the cell.
What is needed is an NVM cell that is small to medium in size, can be produced using a standard CMOS process flow having a single polysilicon layer, and exhibits high endurance.